Profile

Building faster and more reliable EDA workflows

I am an EDA software engineer focused on optimization algorithms, transistor-level automation, and performance-critical physical design systems.

A full PDF resume with detailed experience, education, research, and awards is available here.

Current focus
My recent work combines production software engineering with research-driven optimization.

Developing and improving netlist optimization, topology refinement, and validation logic for advanced-node standard-cell layout automation.

Building Python and C++ hybrid EDA engines for performance-sensitive transistor-level physical design workflows.

Accelerating placement exploration with CUDA-based candidate evaluation and consistency validation between CPU and GPU flows.

Highlights
A few measurable outcomes from recent engineering and research work.
Achieved up to 800× runtime improvement through warp-level CUDA parallelization.
Delivered 33% runtime reduction and 15% EDP improvement in AI-based logic synthesis parameter optimization research.
Published semiconductor conference research and received a Best Paper Award at KCS 2025.

I am a software engineer focused on performance optimization and system design in VLSI/EDA and Scientific Computing. I primarily work with C++ and Python, with experience in implementing complex algorithms and designing large-scale system architectures. Recently, I have also been interested in AI/ML and LLM-based agent development.

Languages
Python 3.11+C++TypeScript
Domain Expertise
VLSI/EDA (Netlist Optimizing, Cell-level Placement)CFD (OpenFOAM)AI (RL, LLM)
Tools
Design CompilerIC CompilerVerdiLinuxDockerParaviewIsaac SimGitPerforce
Experience
Hands-on work across EDA product engineering, academic research, and startup execution.

EDA Engineer

Axion Co., Ltd.

Jun. 2025 – Present · Pangyo, Republic of Korea

  • Researching and developing optimization algorithms for 4nm standard-cell layout automation.
  • Building core software for transistor-level placement, candidate evaluation, and constraint validation.
  • Improving production EDA workflows with Python/C++ hybrid engines and GPU-accelerated placement components.

Undergraduate Student Researcher

VLSiCAD Lab, Sejong University

Aug. 2024 – Dec. 2024 · Seoul, Republic of Korea

  • Researched Design Compiler parameter optimization using genetic algorithms.
  • Compared optimization behavior across selection, mutation, and initial-population strategies.
  • Measured performance gains that reduced runtime and improved energy-delay product.

Cofounder, H/W Engineer

PLANTNER INC.

Jan. 2023 – Nov. 2023 · Seoul, Republic of Korea

  • Researched plant growth hormone measurement approaches and hardware product concepts.
  • Planned SDG-aligned international cooperation initiatives and support proposals with KOICA.
  • Helped secure KRW 200M in funding through KOICA CTS Seed Program selection.
Education
Formal training in electrical engineering, design automation, and systems thinking.

B.S. in Electrical and Information Engineering

Sejong University

Mar. 2020 – Feb. 2026

  • Total GPA: 4.25/4.5
  • Major GPA: 4.44/4.5
  • Graduated Summa Cum Laude.
Publications
Research output closely tied to optimization and EDA tooling.

Circuit-Similarity-Based Parameter Optimization for Logic Synthesis Tools

Korean Conference on Semiconductors (KCS), 2025

Authored with Jinil An and Daijoon Hyun, and recognized with a Best Paper Award.

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