Engineering for semiconductor design and reliable systems
I am growing as a semiconductor design engineer through work in optimization algorithms, transistor-level design, and performance-oriented system implementation.
A full PDF resume with detailed experience, education, research, and awards is available here.
Developing and improving netlist optimization, topology refinement, and validation logic for advanced-node standard-cell layout automation.
Building Python and C++ based optimization engines for performance-sensitive transistor-level design problems.
Accelerating placement exploration with CUDA-based candidate evaluation and consistency validation between CPU and GPU flows.
I am an engineer interested in semiconductor design, scientific computing, performance optimization, and system-level problem solving. I primarily work with C++ and Python, with experience implementing complex algorithms and building practical engineering tools. Recently, I have also been interested in AI/ML and LLM-based agent development.
Semiconductor Design Engineer
Axion Co., Ltd.
Jun. 2025 – Present · Pangyo, Republic of Korea
- Researching and developing optimization algorithms for 4nm standard-cell layout automation.
- Building core software for transistor-level placement, candidate evaluation, and constraint validation.
- Improving design automation and optimization flows with Python/C++ hybrid engines and GPU-accelerated placement components.
Undergraduate Student Researcher
VLSiCAD Lab, Sejong University
Aug. 2024 – Dec. 2024 · Seoul, Republic of Korea
- Researched Design Compiler parameter optimization using genetic algorithms.
- Compared optimization behavior across selection, mutation, and initial-population strategies.
- Measured performance gains that reduced runtime and improved energy-delay product.
Cofounder, H/W Engineer
PLANTNER INC.
Jan. 2023 – Nov. 2023 · Seoul, Republic of Korea
- Researched plant growth hormone measurement approaches and hardware product concepts.
- Planned SDG-aligned international cooperation initiatives and support proposals with KOICA.
- Helped secure KRW 200M in funding through KOICA CTS Seed Program selection.
B.S. in Electrical and Information Engineering
Sejong University
Mar. 2020 – Feb. 2026
- Total GPA: 4.25/4.5
- Major GPA: 4.44/4.5
- Graduated Summa Cum Laude.
Circuit-Similarity-Based Parameter Optimization for Logic Synthesis Tools
Korean Conference on Semiconductors (KCS), 2025
Authored with Jinil An and Daijoon Hyun, and recognized with a Best Paper Award.
Best Paper Award
KCS / VLSI CAD
Open certificate
Encouragement Award
AI Semiconductor Idea/Design Contest / IITP
Open certificate
1st place
IT Creative Challenge / IEIE
Open certificate
2 Years Full-funded Scholarship
Korea Leaders Scholarship Foundation (KLSF)
Open certificate
Promising Student Startup Team 300 Certification
Ministry of Education
Open certificate